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ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. general description the ds1856m dual, temperature-controlled, nonvolatile (nv) variable resistors with three monitors consists of two 256-position, linear, variable resistors; three analog monitor inputs (mon1, mon2, mon3); and a direct-to- digital temperature sensor. the device provides an ideal method for setting and temperature-compensating bias voltages and currents in control applications using minimal circuitry. the variable resistor settings are stored in eeprom memory and can be accessed over the 2-wire serial bus. the ds1856m includes 128 bytes of eeprom memory at a2h slave address, table 00/01. the ds1856m also includes three-levels of password protection. the ds1856-01 includes 256 bytes of a0h eeprom memo- ry. the ds1856b-m50+ and ds1856e-m50+ are drop- in replacements for the ds1856b-050+ and ds1866e-050+, respectively. the enhancements include 256 bytes of eeprom at a0h; selectable mon2, mon3 references; and a 13-bit adc. these are backward compatible by default with the ds1856b-050+/ds1856e-050+. applications optical transceivers optical transponders instrumentation and industrial controls rf power amps diagnostic monitoring features ? sff-8472 compatible ? 13-bit adc ? two linear, 256-position, nonvolatile temperature-controlled variable resistors with 2c resolution ? three levels of security ? access to monitoring and id information configurable with separate device addresses ? 2-wire serial interface ? two buffers with ttl/cmos-compatible inputs and open-drain outputs ? operates from a 3.3v or 5v supply ? -40c to +95c operating temperature range 19-6395; rev 0; 7/12 evaluation kit available sda 1 2 3 4 5 6 7 8 16 0.1 f 15 14 13 12 11 10 9 scl out1 in1 out2 in2 n.c. gnd v cc h1 l1 h0 l0 mon3 mon2 mon1 rx power* diagnostic inputs to laser modulation control to laser bias control decoupling capacitor tx power* tx bias* *satisfies sff-8472 compatibility v cc v cc = 3.3v 4.7k 4.7k tx-fault los 2-wire interface ds1856m typical operating circuit ordering information appears at end of data sheet.
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 2 absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages relative to ground.) voltage range on v cc ..........................................-0.5v to +6.0v voltage range on inputs ..........................-0.5v to (v cc + 0.5v)* voltage range on resistor inputs ............-0.5v to (v cc + 0.5v)* current into resistors............................................................5ma continuous power dissipation (t a = +70?) csbga (derate 16.1?/w above +70?) ..................887.1mw tssop (derate 11.1?/w above +70?) ...................888.9mw operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? lead temperature (tssop only; soldering, 10s) ............+300? soldering temperature (reflow) .......................................+260? recommended operating conditions (t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc (note 4) 1 2 ma input leakage i il -200 +200 na low-level output voltage (sda, out1, out2) v ol1 3ma sink current 0 0.4 v full-scale input (mon1, mon2, mon3) at factory setting (note 5) 2.4875 2.5 2.5125 v full-scale v cc monitor at factory setting (note 6) 6.5208 6.5536 6.5864 v i/o capacitance c i/o 10 pf digital power-on reset pod pod < poa (note 7) 1.0 2.5 v analog power-on reset poa 1.875 2.65 v dc electrical characteristics (v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted.) (note 3) * not to exceed 6.0v. parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.85 5.50 v input logic 1 (sda, scl) v ih (note 2) 0.7 x v cc v cc + 0.3 v input logic 0 (sda, scl) v il (note 2) -0.3 +0.3 x v cc v resistor inputs (l0, l1, h0, h1) -0.3 v cc + 0.3 v resistor current i res -3 +3 ma high-impedance resistor current i roff 0.001 0.1 a input logic 1 2 input logic levels (in1, in2) input logic 0 0.8 v
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 3 parameter symbol conditions min typ max units thermometer error t err -40c to +95c 3.0 c digital thermometer (v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units eeprom writes +70c (note 7) 50,000 writes nonvolatile memory characteristics (v cc = 2.85v to 5.5v, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units adc resolution 13 bits inl t a = +25c -3 +3 lsb dnl -1 +1 lsb input resolution vmon 610 v supply resolution v cc 1.6 mv input/supply accuracy (mon1, mon2, mon3, v cc ) a cc at factory setting 0.25 0.5 % fs (full scale) update rate for mon1, mon2, mon3, temp, or v cc t frame 32 40 ms input/supply offset (mon1, mon2, mon3, v cc ) v os (note 6) 0 1 lsb mon1, mon2, mon3 (note 5) 2.5 factory setting full scale v cc (note 5) 6.5536 v temperature lsb weighting 1/256 c analog voltage monitoring (v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted.) (note 3) parameter conditions min typ max units position 00h resistance (50k ) t a = +25c 0.72 0.9 1.08 k position ffh resistance (50k ) t a = +25c 40 50 60 k inl (note 8) -2 +2 lsb dnl (note 9) -1 +1 lsb temperature coefficient (note 10) 50 ppm/c analog resistor characteristics (v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted.) (note 3)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 4 parameter symbol conditions min typ max units scl clock frequency f scl 0 400 khz bus free time between stop and start condition t buf 1.3 s hold time (repeated) start condition t hd:sta (note 11) 0.6 s low period of scl clock t low 1.3 s high period of scl clock t high 0.6 s data hold time t hd:dat (notes 12, 13) 0 0.9 s data setup time t su:dat 100 ns start setup time t su:sta 0.6 s rise time of both sda and scl signals t r (note 14) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 14) 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 s capacitive load for each bus c b (note 14) 400 pf eeprom write time t w 10 20 ms ac electrical characteristics (v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted. see figure 5.) (note 3) note 1: all voltages are referenced to ground. note 2: i/o pins of fast-mode devices must not obstruct the sda and scl lines if v cc is switched off. note 3: limits are 100% production tested at t a = +25? and/or t a = +95?. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 4: sda and scl are connected to v cc and all other input signals are connected to well-defined logic levels. note 5: full scale is user programmable. the maximum voltage that the mon inputs read is approximately full scale, even if the voltage on the inputs is greater than full scale. note 6: this voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum v cc voltage. note 7: guaranteed by design. note 8: inl is the difference of measured value from expected value at dac position. the expected value is a straight line from measured minimum position to measured maximum position. note 9: dnl is the deviation of an lsb dac setting change vs. the expected lsb change. the expected lsb change is the slope of the straight line from measured minimum position to measured maximum position. note 10: see the typical operating characteristics . note 11: after this period, the first clock pulse is generated. note 12: the maximum t hd:dat only has to be met if the device does not stretch the low period (t low ) of the scl signal. note 13: a device must internally provide a hold time of at least 300ns for the sda signal (see the v ih_min of the scl signal) to bridge the undefined region of the falling edge of scl. note 14: c b ?otal capacitance of one bus line, timing referenced to 0.9 x v cc and 0.1 x v cc .
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection supply current vs. temperature ds1856m toc01 temperature (c) supply current (ma) 85 60 35 10 -15 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.3 -40 v cc = 5.5v sda = scl = v cc v cc = 2.85v supply current vs. supply voltage ds1856m toc02 v cc (v) supply current (ma) 3.85 4.85 3.35 4.35 5.35 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 2.85 sda = scl = v cc -40c +25c +95c resistance vs. setting ds1856m toc03 setting (dec) resistance (k i ) 100 200 50 150 250 5 10 15 20 25 30 35 40 45 50 0 0 50k i version active supply current vs . scl frequency ds1856m toc04 scl frequency (khz) active supply current ( a) 300 200 100 720 740 760 780 800 700 0 400 sda = v cc resistor 0 inl (lsb) vs. setting ds1856m toc05 setting (dec) resistor 0 inl (lsb) 250 25 50 75 100 125 150 175 200 225 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 resistor 0 dnl (lsb) vs. setting ds1856m toc06 setting (dec) resistor 0 dnl (lsb) 250 25 50 75 100 125 150 175 200 225 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 resistor 1 inl (lsb) vs. setting ds1856m toc07 setting (dec) resistor 1 inl (lsb) 250 25 50 75 100 125 150 175 200 225 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 resistor 1 dnl (lsb) vs. setting ds1856m toc08 setting (dec) resistor 1 dnl (lsb) 250 25 50 75 100 125 150 175 200 225 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 resistance vs . power-up voltage ds1856m toc09 power-up voltage (v) resistance (k ) 234 1 30 20 40 50 60 70 80 90 100 110 120 0 10 05 programmed resistance (80h) >1m 5 typical operating characteristics (v cc = 5.0v, t a = +25?, unless otherwise noted.)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 6 6 position 00h resistance vs. temperature ds1856m toc10 temperature (c) position 00h resistance ( i ) 80 65 35 50 -10 5 20 -25 820 840 860 880 900 920 940 960 980 1000 800 -40 95 position ffh resistance vs. temperature ds1856m toc11 temperature (c) position ffh resistance (k i ) 80 65 35 50 -10 5 20 -25 48.00 46.00 -40 95 46.25 46.50 46.75 47.00 47.50 47.25 47.75 2 . 0 1 . 5 1 . 0 0 . 5 02 . 5 -2 -1 0 1 2 3 -3 input voltage (v) monitor inl (lsb) ds1856m toc13 monitor inl (lsb) vs. input voltage monitor dnl (lsb) vs. input voltage ds1856m toc14 input voltage (v) monitor dnl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 temperature coefficient vs. resisitor setting ds1856m toc12 resistor setting (dec) temperature coefficient (ppm) 250 200 150 100 50 50 100 150 200 250 300 350 0 0 +25c to +95c +25c to -40c typical operating characteristics (continued) (v cc = 5.0v, t a = +25?, unless otherwise noted.)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 7 pin ball name function 1 b2 sda 2-wire serial data i/o pin. transfers serial data to and from the device. 2 a2 scl 2-wire serial clock input. clocks data into and out of the device. 3 c3 out1 open-drain buffer output 4 a1 in1 ttl/cmos-compatible input to buffer 5 b1 out2 open-drain buffer output 6 c2 in2 ttl/cmos-compatible input to buffer 7 c1 n.c. no connection 8 d1 gnd ground 9 d3 mon1 external analog input 10 d4 mon2 external analog input 11 c4 mon3 external analog input 12 d2 l0 low-end resistor 0 terminal. it is not required that the low-end terminals be connected to a potential less than the high-end terminals of the corresponding resistor. voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, v cc , or go below ground. 13 b3 h0 high-end resistor 0 terminal. it is not required that the high-end terminals be connected to a potential greater than the low-end terminals of the corresponding resistor. voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, v cc , or go below ground. 14 b4 l1 low-end resistor 1 terminal 15 a4 h1 high-end resistor 1 terminal 16 a3 v cc supply voltage pin/bump descriptions a top view b c d 13 24 mon3 out1 in2 mon1 l0 gnd n.c. l1 h0 sda out2 h1 v cc scl in1 mon2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sda v cc h1 l1 h0 l0 mon3 mon2 mon1 + tssop scl out1 in2 in1 out2 n.c. gnd ds1856m pin/bump configurations
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 8 detailed description the user can read the registers that monitor the v cc , mon1, mon2, mon3, and temperature analog signals. after each signal conversion, a corresponding bit is set that can be monitored to verify that a conversion has occurred. the signals also have alarm and warning flags that notify the user when the signals go above or below the user-defined value. interrupts can also be set for each signal. the position values of each resistor can be indepen- dently programmed. the user can assign a unique value to each resistor for every 2? increment over the -40? to +102? range. two buffers are provided to convert logic-level inputs into open-drain outputs. typically, these buffers are used to implement transmit (tx) fault and loss-of-signal (los) functionality. additionally, out1 can be asserted in the event that one or more of the monitored values go beyond user-defined limits. monitored signals each signal (v cc , mon1, mon2, mon3, and tempera- ture) is available as a 16-bit value with 13-bit accuracy (left-justified) over the serial bus. see table 1 for signal full scales and table 2 for signal format. the three lsbs are internally masked with 0s. the signals are updated every frame rate (t frame ) in a round-robin fashion. the comparison of all five signals with the high and low user-defined values are done automatically. the corre- sponding flags are set to 1 within a specified time of the occurrence of an out-of-limit condition. calculating signal values the lsb = 100? for v cc , and the lsb = 38.147? for the mon signals when using factory default settings. to calculate v cc , convert the unsigned 16-bit value to decimal and multiply by 100?. to calculate mon1, mon2, or mon3, convert the unsigned 16-bit value to decimal and multiply by 38.147?. to calculate the temperature, treat the two? comple- ment value binary number as an unsigned binary num- ber, then convert to decimal and divide by 256. if the result is greater than or equal to 128, subtract 256 from the result. temperature: high byte: -128 c to +127 c signed; low byte: 1/256 c. signal +fs signal +fs (hex) -fs signal -fs (hex) temperature +127.984 c 7ffc -128 c 8000 v cc 6.5528v fff8 0v 0000 mon1 2.4997v fff8 0v 0000 mon2 2.4997v fff8 0v 0000 mon3 2.4997v fff8 0v 0000 table 1. scales for monitor channels at factory setting signal format v cc unsigned mon1 unsigned mon2 unsigned mon3 unsigned temperature twos complement table 2. signal comparison msb 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 lsb 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb (bin) lsb (bin) voltage (v) 10000000 10000000 3.29 11000000 11111000 4.94 monitor/v cc bit weights v cc conversion examples s2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 msb (bin) lsb (bin) voltage (v) 11000000 00000000 1.875 10000000 10000000 1.255 temperature bit weights monitor conversion example msb (bin) lsb (bin) temperature ( c) 01000000 00000000 +64 01000000 00001111 +64.059 01011111 00000000 +95 11110110 00000000 -10 11011000 00000000 -40 temperature conversion examples
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 9 a0h eeprom 256 x 8 address address address r/w r/w txf data bus r/w txf rxl los wrprot_aux sda scl in1 out1 2-wire interface mint inv1 tx fault in2 mon2 mon1 mon2 ref v cc gnd out2 inv2 eeprom 128 x 8 bit standards address table select table select r/w eeprom 72 x 8 bit 80h-c7h table 04 resistor 0 lookup table eeprom 96 x 8 bit 00h-5fh limits sram 32 x 8 bit 60h-7fh temp index alarm flags warning flags mux ctrl measurement address table select r/w eeprom 72 x 8 bit 80h-c7h table 05 resistor 1 lookup table temp index monitors limit high monitors limit low table select temp index mint (bit) internal temp v cc mux 13-bit adc internal calibration a/d ctrl v cc v cc comparator measurement alarm flags warning flags monitors limit low monitors limit high comp ctrl interrupt mint table 03 eeprom 80h-b7h vendor device address address table select masking (temp, v cc , mon1, mon2, mon3) inv2 (bit) inv1 (bit) resistor 0 256 positions l0 h0 register register resistor 1 256 positions l1 h1 right shifting r/w mon3 mon3 ref v cc ds1856m figure 1. block diagram
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 10 variable resistors the value of each variable resistor is determined by a temperature-addressed lookup table, which can assign a unique value (00h to ffh) to each resistor for every 2? increment over the -40? to +102? range (see table 3). see the temperature conversion section for more information. the variable resistors can also be used in manual mode. if the ten bit equals 0, the resistors are in manu- al mode and the temperature indexing is disabled. the user sets the resistors in manual mode by writing to addresses 82h and 83h in table 03 to control resistors 0 and 1, respectively. memory description the ds1856m 2-wire interface uses 8-bit addressing, which allows up to 256 bytes to be addressed tradi- tionally on a given 2-wire slave address. however, since the a2h memory contains more than 256 bytes, a table scheme is used. the lower 128 bytes of the a2h memory, memory locations 00h to 7fh, function as expected and are independent of the currently select- ed table. byte 7fh is the table select byte. this byte determines which memory table is accessed by the 2- wire interface when address locations 80h?fh are accessed. memory locations 80h?fh are accessible only through the a2h memory address. valid values for the table select byte are shown in table 4. before attempting to read and write any of the bits or bytes mentioned in this section, it is important to look at the memory map provided in a subsequent section to verify what level of password is required. password protection the ds1856m uses two 4-byte passwords to achieve three levels of access to various memory locations. the three levels of access are: user access: this is the default state after power-up. it allows read access to standard monitoring and sta- tus functions. level 1 access: this allows access to customer data table (tables 00 and 01) in addition to every- thing granted by user access. this level is granted by entering password 1 (pw1). level 2 access: this allows access to all memory, settings, and features, in addition to everything granted by level 1 and user access. this level is granted by entering password 2 (pw2). to obtain a particular level of access, the correspond- ing password must be entered in the password entry (pwe) bytes located in the a2h memory at 7bh to 7eh. the value entered is compared to both the pw1 and pw2 settings located in table 03, bytes b0h to b3h and table 03, bytes b4h to b7h, respectively, to determine if access should be granted. access is granted until the password is changed or until power is cycled. writing pwe can be done with any level of access, although pwe can never be read. writing pw1 and pw2 requires pw2 access. however, pw1 and pw2 can never be read, even with pw2 access. on power-up, pwe is set to all 1s (ffffh). as long as neither of the passwords are ever changed to ffffh, then user access is the power-up default. likewise, password protection can be intentionally disabled by setting the pw2 password to ffffh. table 3. lookup table address for corresponding temperature values table select byte table name 00 01 eeprom memory 02 does not exist 03 configuration 04 resistor 0 lookup table 05 resistor 1 lookup table table 4. table select byte temperature (c) corresponding lookup table address <-40 80h -40 80h -38 81h -36 82h -34 83h +98 c5h +100 c6h +102 c7h >+102 c7h
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 11 memory map table 5 is the legend used in the memory map to indi- cate the access level required for read and write access. each table in the memory map begins with a higher level view of a particular portion of the memory showing information such as row (8 bytes) and byte names. the tables are then followed, where applicable, by an expanded bytes table, which shows bit names and val- ues. furthermore, both tables use the permission leg- end to indicate the access required on a row, byte, and bit level. the memory map is followed by a register description section, which describes bytes and bits in further detail. table 00h/01h eeprom memory (128 bytes) 80h ffh 255 ff 127 a0h 7f 128 80 183 b7 199 c7 200 c8 lower memory table select byte password entry (pwe) (4 bytes) 00h 7fh 2-wire addrress a2h (default) a2h memory a0h memory note 1: a2h memory is addressed using the 2-wire slave address, a2h. note 2: tables 00h and 01h access the same physical memory. note 3: table 02h does not exist. note 4: a0h memory is addressed using the 2-wire slave address, a0h. dec hex 0 255 0 0 table 03h configuration table 80h b7h table 04h resistor 0 lookup table (72 bytes) 80h c7h table 05h resistor 1 lookup table (72 bytes) 80h c7h reserved and calibration constants reserved and calibration constants f0h ffh f0h ffh figure 2. memory organization permission read write <0> at least one byte in the row is different than the rest of the row, so look at each byte separately for permissions. <1> all pw2 <2> all na <3> all all (the part also writes to this byte.) <4> pw2 pw2 + mode_bit <5> all all <6> na all <7> pw1 pw1 <8> pw2 pw2 <9> na pw2 <10> pw2 na <11> all pw1 table 5. password permission
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 12 a2h lower memory word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00 <1> threshold 0 temp alarm hi temp alarm lo temp warn hi temp warn lo 08 <1> threshold 1 v cc alarm hi v cc alarm lo v cc warn hi v cc warn lo 10 <1> threshold 2 mon1 alarm hi mon1 alarm lo mon1 warn hi mon1 warn lo 18 <1> threshold 3 mon2 alarm hi mon2 alarm lo mon2 warn hi mon2 warn lo 20 <1> threshold 4 mon3 alarm hi mon3 alarm lo mon3 warn hi mon3 warn lo 28 <1> user rom ee ee ee ee ee ee ee ee 30 <1> user rom ee ee ee ee ee ee ee ee 38 <1> user rom ee ee ee ee ee ee ee ee 40 <1> user rom ee ee ee ee ee ee ee ee 48 <1> user rom ee ee ee ee ee ee ee ee 50 <1> user rom ee ee ee ee ee ee ee ee 58 <1> user rom ee ee ee ee ee ee ee ee 60 <2> values 0 temp value vcc value mon1 value mon2 value 68 <0> values 1 <2> mon3 value <2> reserved <2> reserved <0> status <3> update 70 <2> alrm wrn alarm 1 alarm 0 reserved reserved warn 1 warn 0 reserved reserved 78 <0> table select <6> reserved <6> reserve d <6> reserve d <6> pwe msb <6> pwe lsb <5> tbl sel expanded bytes bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 byte (hex) byte name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user ee ee ee ee ee ee ee ee ee temp alarm s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 temp warn s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 volt alarm 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 volt warn 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 28 user rom ee ee ee ee ee ee ee ee 30 user rom ee ee ee ee ee ee ee ee 38 user rom ee ee ee ee ee ee ee ee 40 user rom ee ee ee ee ee ee ee ee 48 user rom ee ee ee ee ee ee ee ee 50 user rom ee ee ee ee ee ee ee ee 58 user rom ee ee ee ee ee ee ee ee memory map a0h memory (at 2-wire address a0h) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00Cff <1> ee ee ee ee ee ee ee ee ee
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 13 memory map (continued) a2h table 00/01 word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80Cff <7> ee ee ee ee ee ee ee ee ee expanded bytes bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 byte (hex) byte name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 60 temp value s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 62 v cc value 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 64 mon1 value 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 66 mon2 value 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 68 mon3 value 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 6e status <2> rhiz <11> softhiz <2> reserve <2> reserve <2> reserve <2> txf <2> rxl <2> rdyb 6f update temp rdy v cc rdy mon1 rdy mon2 rdy mon3 rdy reserved reserved reserved 70 alarm 1 temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo 71 alarm 0 mon3 hi mon3 lo reserved reserved reserved reserved reserved mint 74 warn 1 temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo 75 warn 0 mon3 hi mon3 lo reserved reserved reserved reserved reserved reserved 7b pwe msb 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7d pwe lsb 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 7f tbl sel 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 14 a2h table 03 (configuration) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <0> config 0 <8> mode <4> tindex <4> res0 <4> res1 <8> reserve <8> reserve <8> reserve <8> reserve 88 <8> config 1 int enable config reserved reserved chip addr reserved rshift 1 rshift 0 90 <8> scale 0 reserved vcc scale mon1 scale mon2 scale 98 <8> scale 1 mon3 scale reserved reserved reserved a0 <8> offset 0 reserved vcc offset mon1 offset mon2 offset a8 <8> offset 1 mon3 offset reserved reserved internal temp offset* b0 <9> pwd value pw1 msb pw1 lsb pw2 msb pw2 lsb expanded bytes bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 byte (hex) byte name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 mode reserved reserved reserved reserved reserved reserved ten aen 81 tindex 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 82 res0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 83 res1 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 88 int enable temp vcc mon1 mon2 mon3 reserved reserved reserved 89 config wrprot_ aux reserved reserved reserved mon3 ref mon2 ref inv 1 inv 2 8c reserved reserved reserved reserved reserved reserved reserved reserved reserved 8e rshift 1 reserved mon1 2 mon1 1 mon1 0 reserved mon2 2 mon2 1 mon2 0 8f rshift 0 reserved mon3 2 mon3 1 mon3 0 reserved reserved reserved reserved 92 v cc scale 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 94 mon1 scale 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 96 mon2 scale 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 98 mon3 scale 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a2 v cc offset s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 a4 mon1 offset s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 a6 mon2 offset s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 a8 mon3 offset s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ae temp offset* s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 b0 pw1 msb 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b2 pw1 lsb 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b4 pw2 msb 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b6 pw2 lsb 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 * the final result must be xored with bb40h. memory map (continued)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 15 a2h table 04 (lookup table for resistor 0) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut 88 <8> lut 90 <8> lut 98 <8> lut a0 <8> lut a8 <8> lut b0 <8> lut b8 <8> lut c0 <8> lut c8 empty empty empty empty empty empty empty empty d0 empty empty empty empty empty empty empty empty d8 empty empty empty empty empty empty empty empty e0 empty empty empty empty empty empty empty empty e8 empty empty empty empty empty empty empty empty f0 reserved reserved reserved reserved reserved reserved reserved reserved f8 <10> res0 data resistor 0 calibration constants (see data sheet table 6) expanded bytes byte (hex) byte name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 80C c7 res0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 f8Cff res0 data resistor 0 calibration constants (see data sheet table 6 for weighting) memory map (continued)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 16 a2h table 05 (lookup table for resistor 1) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut 88 <8> lut 90 <8> lut 98 <8> lut a0 <8> lut a8 <8> lut b0 <8> lut b8 <8> lut c0 <8> lut c8 empty empty empty empty empty empty empty empty d0 empty empty empty empty empty empty empty empty d8 empty empty empty empty empty empty empty empty e0 empty empty empty empty empty empty empty empty e8 empty empty empty empty empty empty empty empty f0 reserved reserved reserved reserved reserved reserved reserved reserved f8 <10> res1 data resistor 1 calibration constants (see data sheet table 6) expanded bytes byte (hex) byte name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 80C c7 res1 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 f8Cff res1 data resistor 1 calibration constants (see data sheet table 6 for weighting) memory map (continued)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 17 register descriptions name of row ? name of byte .............

? name of byte .............

threshold 0 ? temp high alarm ..... <7fffh> temperature measurements above this two's complement threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. ? temp low alarm ....... <8000h> temperature measurements below this two's complement threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit. ? temp high warning . <7fffh> temperature measurements above this two's complement threshold set its corresponding warning bit. measurements below this threshold clear the warning bit. ? temp low warning .. <8000h> temperature measurements below this two's complement threshold set its corresponding warning bit. measurements above this threshold clear the warning bit. threshold 1 ? v cc high alarm ........ voltage measurements of the v cc input above this unsigned threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. ? v cc low alarm .......... <<0000h> voltage measurements of the v cc input below this unsigned threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit. ? v cc high warning .... voltage measurements of the v cc input above this unsigned threshold set its corresponding warning bit. measurements below this threshold clear the warning bit. ? v cc low warning ..... <<0000h> voltage measurements of the v cc input below this unsigned threshold set its corresponding warning bit. measurements above this threshold clear the warning bit. threshold 2 ? mon1 high alarm ..... voltage measurements of the mon1 input above this unsigned threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. ? mon1 low alarm ...... <0000h> voltage measurements of the mon1 input below this unsigned threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit. ? mon1 high warning . voltage measurements of the mon1 input above this unsigned threshold set its corresponding warning bit. measurements below this threshold clear the warning bit. ? mon1 low warning .. <0000h> voltage measurements of the mon1 input below this unsigned threshold set its corresponding warning bit. measurements above this threshold clear the warning bit.
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 18 threshold 3 ? mon2 high alarm ..... voltage measurements of the mon2 input above this unsigned threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. ? mon2 low alarm ...... <0000h> voltage measurements of the mon2 input below this unsigned threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit. ? mon2 high warning . voltage measurements of the mon2 input above this unsigned threshold set its corresponding warning bit. measurements below this threshold clear the warning bit. ? mon2 low warning .. <0000h> voltage measurements of the mon2 input below this unsigned threshold set its corresponding warning bit. measurements above this threshold clear the warning bit. threshold 4 ? mon3 high alarm ..... voltage measurements of the mon3 input above this unsigned threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. ? mon3 low alarm ...... <0000h> voltage measurements of the mon3 input below this unsigned threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit. ? mon3 high warning . voltage measurements of the mon3 input above this unsigned threshold set its corresponding warning bit. measurements below this threshold clear the warning bit. ? mon3 low warning .. <0000h> voltage measurements of the mon3 input below this unsigned threshold set its corresponding warning bit. measurements above this threshold clear the warning bit. user rom ? user rom ................. <00h> nonvolatile eeprom memory. a2d value 0 ? temp meas ................ <0000h> the signed two's complement direct-to-temperature measurement. ? v cc meas ................... <0000h> unsigned voltage measurement. ? mon1 meas ................ <0000h> unsigned voltage measurement. ? mon2 meas ................ <0000h> unsigned voltage measurement. register descriptions (continued)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 19 a2d value 1 ? mon3 meas .......... <0000h> unsigned voltage measurement. ? reserved .............. <0000h> ? status ................... a) rhiz.............. <1b> high when resistor outputs are high impedance. b) soft hiz ........ <0b> setting this bit will make resistor outputs high impedance. c) reserved ...... <0b> d) txf ............. reflects the logic level to be output on pin out1. e) rxl ............. reflects the logic level to be output on pin out2. f) rdyb............. < v cc dependent > ready bar. when the supply is above the power-on-analog (poa) trip point, this bit is active low. thus, this bit reads a logic one if the supply is below poa or too low to communicate over the 2-wire bus. ? update ................. <00h> status of completed conversions. at power-on, these bits are cleared and will be set as each conversion is completed. these bits can be cleared so that a completion of a new conversion may be verified. a) temp rdy .... temperature conversion is ready. b) v cc rdy....... v cc conversion is ready. c) mon1 rdy.... mon1 conversion is ready. d) mon2 rdy.... mon2 conversion is ready. e) mon3 rdy.... mon3 conversion is ready. status ? alarm 0 ................. <10h> high alarm status bits. a) temp hi ....... high alarm status for temperature measurement. b) temp lo ...... low alarm status for temperature measurement. c) v cc hi ........ high alarm status for v cc measurement. d) v cc lo ........ low alarm status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. e) mon1 hi..... high alarm status for mon1 measurement. f) mon1 lo .... low alarm status for mon1 measurement. g) mon2 hi..... high alarm status for mon2 measurement. h) mon2 lo .... low alarm status for mon2 measurement. ? alarm 1 ................. <00h> low alarm status bits. a) mon3 hi..... high alarm status for mon3 measurement. b) mon3 lo .... low alarm status for mon3 measurement. c) mint ............. maskable interrupt. if an alarm is present and the alarm is enabled then this bit is high. otherwise this bit is a zero. ? reserved .............. <00h>. ? warning 0 ............. <00h> high warning status bits. a) temp hi ....... high warning status for temperature measurement. b) temp lo ...... low warning status for temperature measurement. c) v cc hi ....... high warning status for v cc measurement. register descriptions (continued)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 20 table select ? reserved ....................

<00h> ? pwe ...........................

password entry. there are two passwords for the ds1856m. the lower level password (pw1) has all the access of a normal user plus those made available with pw1. the higher level password (pw2) has all of the access of pw1 plus those made available with pw2. the value of the password reside in ee inside of pw2 memory. ? tbl sel ...................... <00h> table select. the upper memory tables of the ds1856m are accessible by writing the correct table value in this register. if the device is configured to have a table 01h then writing a 00h or a 01h in this byte will access that table. config 0 ? mode .......................... <03h> a) ten.................... at power-on this bit is high, which enables autocontrol of the lut. if this bit is written to a zero then the resistor values are writeable by the user and the lut recalls are disabled. this allows the user to interactively test their modules by manually writing resistor values. the resistors will update with the new value at the end of the write cycle. thus both registers (res0 and res1) should be written in the same write cycle. the 2-wire stop condition is the end of the write cycle. b) aen ................... at power-on this bit is high, which enables autocontrol of the lut. if this bit is cleared to a zero then the temperature calculated index value ( t index ) is writable by the user and the updates of calculated indexes are disabled. this allows the user to interactively test their modules by controlling the indexing for the lookup tables. the recalled values from the luts will appear in the resistor registers after the next completion of a temperature conversion (just like it would happen in auto mode). both pots will update at the same time (just like it would happen in auto mode). ? t index .......................

<00h> holds the calculated index based on the temperature measurement. this index is used for the address during lookup of tables 4 and 5. . d) v cc lo .............. low warning status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. e) mon1 hi ........... high warning status for mon1 measurement. f) mon1 lo .......... low warning status for mon1 measurement. g) mon2 hi ........... high warning status for mon2 measurement. h) mon2 lo .......... low warning status for mon2 measurement. ? warning 1 ................... <00h> low warning status bits. a) mon3 hi........... high warning status for mon3 measurement. b) mon3 lo........... low warning status for mon3 measurement. register descriptions (continued)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 21 config 1 ? int enable .................. configures the maskable interrupt for the out1 pin. a) temp enable...... temperature measurements, outside of the threshold limits, are enabled to create an active interrupt on the out1 pin. b) v cc enable......... v cc measurements, outside of the threshold limits, are enabled to create an active interrupt on the out1 pin. c) mon1 enable.... mon1 measurements, outside of the threshold limits, are enabled to create an active interrupt on the out1 pin. d) mon2 enable.... mon2 measurements, outside of the threshold limits, are enabled to create an active interrupt on the out1 pin. e) mon3 enable.... mon3 measurements, outside of the threshold limits, are enabled to create an active interrupt on the out1 pin. f) reserved ............ ee. ? config ........................ <00h> configure the memory location and the polarity of the digital outputs. b) reserved ............ a) wrprot_aux when this bit is 1, the a0h memory is write protected. c) reserved ............ d) mon3 ref ........ when 0, mon3 is referenced to gnd. when 1, mon3 is referenced to v cc . e) mon2 ref ........ when 0, mon2 is referenced to gnd. when 1, mon2 is referenced to v cc . f) inv1 .................... enable the inversion of the relationship between in1 and out1. g) inv2 .................... enable the inversion of the relationship between in2 and out2. ? ? right shift 1 ................ allows for right-shifting the final answer of some voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. right shift 0 ................ allows for right-shifting the final answer of some voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. ? res1 ...........................

the base value used for resistor 1 and recalled from table 5 at the memory address found in t index. this register is updated at the end of the temperature conversion. ? reserved ....................

<00h> sram. ? res0 ...........................

the base value used for resistor 0 and recalled from table 4 at the memory address found in t index. this register is updated at the end of the temperature conversion. . register descriptions (continued)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 22 offset 0 ? v cc offset .................. <0000h> allows for offset control of v cc measurement if desired. ? mon1 offset ............. <0000h> allows for offset control of mon1 measurement if desired. ? mon2 offset ............. <0000h> allows for offset control of mon2 measurement if desired. offset 1 ? mon3 offset ............. <0000h> allows for offset control of mon3 measurement if desired. ? temp offset ............... <0000h> allows for offset control of temp measurement if desired. pwd value ? password 1 ................ the pwe value is compared against the value written to this location to enable pw1 access. at power-on, the pwe value is set to all ones. thus writing these bytes to all ones grants pw1 access on power-up without writing the password entry. ? password 2 ................ the pwe value is compared against the value written to this location to enable pw2 access. at power-on, the pwe value is set to all ones. thus writing these bytes to all ones grants pw2 access on power-up without writing the password entry. lut ? res0 ........................... the unsigned value for resistor 0. ? res1 ........................... the unsigned value for resistor 1. scale 0 ? v cc scale ................... controls the scaling or gain of the v cc measurements. ? mon1 scale .............. controls the scaling or gain of the mon1 measurements. ? mon2 scale .............. controls the scaling or gain of the mon2 measurements. scale 1 ? mon3 scale .............. controls the scaling or gain of the mon3 measurements. register descriptions (continued)
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 23 programming the lookup table (lut) the following equation can be used to determine which resistor position setting, 00h to ffh, should be written in the lut to achieve a given resistance at a specific tem- perature. r = the resistance desired at the output terminal c = temperature in degrees celsius u, v, w, x 1 , x 0 , y, z, and are calculated values found in the corresponding lookup tables. the variable x from the equation above is separated into x 1 (the msb of x) and x 0 (the lsb of x). their addresses and lsb values are given below. the variable y is a signed value. all other variables are unsigned. resistor 0 variables are found in table 04, and resistor 1 variables are found in table 05. when shipped from the factory, all other memory loca- tions in the luts are programmed to ffh. table 6. calibration constants internal calibration for monitoring weak receive signals, the ds1856m pro- vides the ability to calibrate the adc full scale to pro- vide optional snr for the range of the receive signals. calibration of the adc is discussed in detail in the application note 3408: ds1856 internal calibration and right shifting (scalable dynamic ranging) . temperature conversion the direct-to-digital temperature sensor measures temperature through the use of an on-chip temperature measurement technique with a -40? to +102? oper- ating range. temperature conversions are initiated upon power-up, and the most recent conversion is stored in memory locations 60h and 61h of the a2h memory, which are updated every t frame . temperature conversions do not occur during an active read or write to memory. the value of each resistor is determined by the tempera- ture-addressed lookup table. the lookup table assigns a unique value to each resistor for every 2? increment with a 1? hysteresis at a temperature transition over the oper- ating temperature range (see figure 3). power-up and low-voltage operation during power-up, the device is inactive until v cc exceeds the digital power-on-reset voltage (pod). at this voltage, the digital circuitry, which includes the 2-wire interface, becomes functional. however, eeprom- backed registers/settings cannot be internally read (recalled into shadow sram) until v cc exceeds the ana- log power-on-reset voltage (poa), at which time the remainder of the device becomes fully functional. once v cc exceeds poa, the rdyb bit in byte 6eh of the a2h memory is timed to go from a 1 to a 0 and indicates when analog-to-digital conversions begin. if v cc ever dips below poa, the rdyb bit reads as a 1 again. once a device exceeds poa and the eeprom is recalled, the values remain active (recalled) until v cc falls below pod. for 2-wire device addresses sourced from eeprom, the device address is a2h until v cc exceeds poa and the eeprom values are recalled. the a0h memory is always available within this voltage window (between pod and the eeprom recall). pos r c rux vxc wxc xx yxc zxc , , () = ?+ ? () +? () ? ? ? ? ? ? () +? () +? () ? ? ? ? ? ? ? 125 25 125 25 2 2 address variable lsb f8h u 2 0 f9h v 20e-6 fah w 100e-9 fbh x 1 2 1 fch x 0 2 -7 fdh y 2e-6 (signed) feh z 10e-9 ffh 2 -2 m6 m5 m4 m3 m2 m1 2 4 6 8 10 12 temperature ( c) memory location increasing temperature decreasing temperature figure 3. lookup table hysteresis
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 24 furthermore, as the device powers up, the v cc lo alarm flag (bit 4 of 70h in a2h memory) defaults to a 1 until the first v cc analog-to-digital conversion occurs and sets or clears the flag accordingly. 2-wire operation clock and data transitions: the sda pin is normal- ly pulled high with an external resistor or device. data on the sda pin may only change during scl- low time periods. data changes during scl-high periods will indicate a start or stop condition depending on the conditions discussed below. see the timing diagrams in figures 4 and 5 for further details. start condition: a high-to-low transition of sda with scl high is a start condition that must pre- cede any other command. see the timing diagrams in figures 4 and 5 for further details. stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read or write sequence, the stop command places the ds1856m into a low-power mode. see the timing dia- grams in figures 4 and 5 for further details. acknowledge: all address and data bytes are trans- mitted through a serial protocol. the ds1856m pulls the sda line low during the ninth clock pulse to acknowledge that it has received each word. standby mode: the ds1856m features a low-power mode that is automatically enabled after power-on, after a stop command, and after the completion of all internal operations. device addressing: the ds1856m must receive an 8-bit device address, the slave address byte, follow- ing a start condition to enable a specific device for a read or write operation. the address is clocked into this part msb to lsb. the address byte consists of either a2h or the value in table 03, 8ch for the a2h memory or a0h for the a0h memory, then the r/ w bit. this byte must match the address pro- grammed into table 03, 8ch or a0h (for the a0h memory). if a device address match occurs, this part will output a zero for one clock cycle as an acknowl- edge and the corresponding block of memory is enabled (see the memory organization section). if the r/ w bit is high, a read operation is initiated. if the r/ w is low, a write operation is initiated (see the memory organization section). if the address does not match, this part returns to a low-power mode. write operations after receiving a matching address byte with the r/ w bit set low, if there is no write protect, the device goes into the write mode of operation (see the memory organization section). the master must transmit an 8- bit eeprom memory address to the device to define the address where the data is to be written. after the byte has been received, the ds1856m transmits a zero for one clock cycle to acknowledge the address has been received. the master must then transmit an 8-bit data word to be written into this address. the ds1856m again transmits a zero for one clock cycle to acknowl- edge the receipt of the data. at this point, the master must terminate the write operation with a stop condi- tion. the ds1856m then enters an internally timed write process t w to the eeprom memory. all inputs are dis- abled during this byte write cycle. page write the ds1856m is capable of an 8-byte page write. a page is any 8-byte block of memory starting with an address evenly divisible by eight and ending with the starting address plus seven. for example, addresses 00h through 07h constitute one page. other pages would be addresses 08h through 0fh, 10h through 17h, 18h through 1fh, etc. a page write is initiated the same way as a byte write, but the master does not send a stop condition after the first byte. instead, after the slave acknowledges the data byte has been received, the master can send up to seven more bytes using the same nine-clock sequence. the master must terminate the write cycle with a stop condition or the data clocked into the ds1856m will not be latched into permanent memory. the address counter rolls on a page during a write. the counter does not count through the entire address space as during a read. for example, if the starting address is 06h and 4 bytes are written, the first byte goes into address 06h. the second goes into address 07h. the third goes into address 00h (not 08h). the fourth goes into address 01h. if 9 bytes or more are written before a stop condition is sent, the first bytes sent are overwritten. only the last 8 bytes of data are written to the page. acknowledge polling: once the internally timed write has started and the ds1856m inputs are disabled, acknowledge polling can be initiated. the process involves transmitting a start condition followed by the device address. the r/ w bit signifies the type of opera- tion that is desired. the read or write sequence will only be allowed to proceed if the internal write cycle has completed and the ds1856m responds with a zero. read operations after receiving a matching address byte with the r/ w bit set high, the device goes into the read mode of
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 25 operation. there are three read operations: current address read, random read, and sequential address read. current address read the ds1856m has an internal address register that maintains the address used during the last read or write operation, incremented by one. this data is main- tained as long as v cc is valid. if the most recent address was the last byte in memory, then the register resets to the first address. once the device address is clocked in and acknowl- edged by the ds1856m with the r/ w bit set to high, the current address data word is clocked out. the master does not respond with a zero, but does generate a stop condition afterwards. single read a random read requires a dummy byte write sequence to load in the data byte address. once the device and data address bytes are clocked in by the master and acknowledged by the ds1856m, the master must gen- erate another start condition. the master now initi- ates a current address read by sending the device address with the r/ w bit set high. the ds1856m acknowledges the device address and serially clocks out the data byte. sequential address read sequential reads are initiated by either a current address read or a random address read. after the master receives the first data byte, the master responds with an acknowledge. as long as the ds1856m receives this acknowledge after a byte is read, the master can clock out additional data words from the ds1856m. after reaching address ffh, it resets to address 00h. the sequential read operation is terminated when the master initiates a stop condition. the master does not respond with a zero. the following section provides a detailed description of the 2-wire theory of operation. 2-wire serial-port operation the 2-wire serial-port interface supports a bidirectional data transmission protocol with device addressing. a device that sends data on the bus is defined as a trans- mitter, and a device that receives data as a receiver. the device that controls the message is called a mas- ter. the devices that are controlled by the master are slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop condi- tions. the ds1856m operates as a slave on the 2-wire bus. connections to the bus are made through the open-drain i/o lines sda and scl. the following i/o terminals control the 2-wire serial port: sda, scl. timing diagrams for the 2-wire serial port can be found in figures 4 and 5. timing information for the 2-wire serial port is provided in the ac electrical characteristics table for 2-wire serial communications. stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 4. 2-wire data transfer protocol
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 26 the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain sta- ble whenever the clock line is high. changes in the data line while the clock line is high will be interpret- ed as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low while the clock is high defines a start condition. stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is sta- ble for the duration of the high period of the clock signal. the data on the line can be changed during the low peri- od of the clock signal. there is one clock pulse per bit of data. figures 4 and 5 detail how data transfer is accom- plished on the 2-wire bus. depending on the state of the r/ w bit, two types of data transfer are possible. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop con- ditions is not limited and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications, a standard mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the ds1856m works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. the master device must generate an extra clock pulse, which is associated with this acknowl- edge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge-related clock pulse. setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the command/control byte. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2) data transfer from a slave transmitter to a mas- ter receiver. the master transmits the first byte (the command/control byte) to the slave. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowl- edge can be returned. figure 5. 2-wire ac characteristics sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection 27 the master device generates all serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. the ds1856m can operate in the following two modes: 1) slave receiver mode: serial data and clock are received through sda and scl, respectively. after each byte is received, an acknowledge bit is trans- mitted. start and stop conditions are recog- nized as the beginning and end of a serial transfer. address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the ds1856m, while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. ordering information part res0/res1 resistance (k ) pin-package ds1856b-m50+ 50/50 16 csbga ds1856b-m50+t&r 50/50 16 csbga ds1856e-m50+ 50/50 16 tssop ds1856e-m50+t&r 50/50 16 tssop + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. note: all devices are specified over the -40? to +95? tem- perature range. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. csbga x16+1 21-0355 90-0334 tssop u16+1 21-0066 90-0117
ds1856m dual, temperature-controlled resistors with calibrated monitors and password protection maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical. characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidan ce. 28 ____________________maxim integrated products, 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/12 initial release

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